ASIC Design Verification Engineer

Required

• 3+ years of experience building and maintaining complex testbenches using UVM/SystemVerilog
• Proven track record with constrained-random generation, functional coverage, and SVA (SystemVerilog Assertions)
• Deep understanding of complex digital logic and the ability to debug intricate hardware/software interactions
• Proficiency in Python for developing scalable automation frameworks, data analysis tools, and regression management suites
• Excellent verbal and written communication skills, ability to collaborate with cross-functional teams
• Strong analytical skills in root-causing failures across RTL, testbench, and environment layers
• Experience spanning initial specification through post-silicon bring-up and validation
• Familiarity with power-aware verification (UPF), formal verification, or hardware-software co-validation
• Domain expertise in ML accelerators, high-speed interconnects (NoCs), or high-bandwidth memory
• Experience with C/C++ for reference model development and enhancement
• Hands-on experience with industry-standard interfaces such as PCIe Gen 5/6, DDR5, or Ethernet
• Interest or experience in leveraging Generative AI and LLMs to accelerate verification workflows, such as automated testbench generation, documentation, or failure log analysis