Principal Engineer, Layout Design

California, Santa Clarafull time

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On Site

senior

H1B: no

Sitimecorporation The Principal Engineer, Layout Design leads custom analog layout design for CMOS and BiCMOS circuits and coordinates offshore layout designers. This role also develops standard layout methodologies and establishes processes to ensure high-quality layout design.

Responsibilities

Collaborate remotely with local and global design and layout teams across multiple design centers and time zones
Lead and perform custom analog layout design at the chip and functional block, block, sub-block, leaf cell, and standard cell levels for CMOS and BiCMOS circuits
Execute schematic-driven layout design while adhering to design constraints
Create area-efficient functional block layouts that meet circuit design requirements
Develop top-chip and block-level floor plans, power distribution networks, shielding structures, and device-matching layouts
Verify layouts and ensure successful DRC, LVS, and ERC signoff
Perform chip-level routing and other layout-related activities
Own chip-chip integration, verification, and tape-out activities
Provide support for additional projects as required by management
Train and mentor junior layout engineers and offshore layout contractors
Contribute to the development of common best practices and workflows across all sites
Help establish and improve processes and procedures to achieve high layout quality

Qualification

Experience with TSMC 180nmSolid working knowledge of DRCUnderstanding of layout conceptsStrong ability to solve device matchingExperience with chip-level integrationMust be able to liftDesired Characteristics & Attributes

Required

BA/BS degree in Layout Design or a related field, or equivalent experience
15+ years of experience in layout design for analog and full-custom digital blocks
Experience with TSMC 180nm, 65nm, 22nm process technologies
Proficiency with layout editing tools in the Cadence Virtuoso design environment
Solid working knowledge of DRC, LVS, and ERC debugging using Cadence PVS or Mentor Calibre
Understanding of layout concepts, including parasitics, matching, crosstalk, layout-dependent effects, latch-up, IR drop, electromigration (EM), and deep N-well and NTN isolation
Strong ability to solve device matching, electromigration, signal integrity, and power distribution challenges while meeting area constraints
Experience with chip-level floorplanning and analog block integration
Experience with chip-level integration, verification, and tape-out
Ability to use productivity-enhancing tools and design scripts to automate and improve workflow efficiency
Must be able to lift, push, and pull up to 5 lbs
Desired Characteristics & Attributes: