Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

Preferred

• Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
• Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)